Zero capacitance bondpad utilizing active negative capacitance

ABSTRACT

The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and thereby effectively eliminate the bondpad capacitance. Values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance and thus produce a negative capacitance approximately equal in magnitude to a unique capacitance associated with the bondpad of a variety of integrated circuits.

FIELD OF THE INVENTION

The present invention generally relates to the field of integratedcircuits, and more particularly to an apparatus for reducing bondpadcapacitance of an integrated circuit.

BACKGROUND OF THE INVENTION

Integrated circuits are employed in most of the digital appliancesutilized on a daily basis by consumers. Integrated circuits may refer toan electronic circuit built onto a single piece of substrate, a chip,and enclosed within a package. Integrated circuits generally perform adesired function or plurality of functions. In the fabrication ofintegrated circuits, bondpads are employed to form the connection fromthe integrated circuit to the package. A package may refer to thehousing of the chip and electrically interconnects the chip with outsidecircuitry.

Referring to FIG. 1, an embodiment of an integrated circuit 100 known tothe art is shown. An integrated circuit 100 may include a siliconsubstrate layer 110 with multiple dielectric layers 120-140 and multiplemetal layers 150-170. The bondpad 180 may refer to the top layer ofmetal and allows a connection from the integrated circuit to thepackage, a package pin for example.

Capacitance occurs between the bondpad 180 and the other metal layers150-170. The amount of capacitance is typically proportional to the areaof the bondpad 180 and increases as the distance between the bondpad 180and the metal layers 150-170 decreases. A drawback caused by thecapacitance associated with the bondpad 180 is a reduction in circuitperformance. As operating speeds have increased, circuit performance hasbeen further reduced by the capacitance associated with the bondpad.

Conventional solutions to reducing the capacitance associated with thebondpad have involved the modification of the layer structure of theintegrated circuit. However, modification of the layer structure isexpensive and typically causes reduced reliability of the circuit.Further, this type of capacitance reduction only provides a minimalreduction in capacitance. Consequently, an improved apparatus and systemfor reducing the bondpad capacitance of an integrated circuit isnecessary.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an apparatus andsystem for reducing bondpad capacitance of an integrated circuit. In anembodiment of the invention, circuitry of the present invention mayproduce a negative capacitance approximately equal in magnitude to thecapacitance associated with the bondpad and thereby effectivelyeliminate the bondpad capacitance. Further, circuitry of the presentinvention may be employed within an integrated circuit without modifyingthe layer structure of the integrated circuit. In an advantageous aspectof the present invention, values of the components of the circuitry maybe selectively and independently chosen to synthesize a variable rangeof negative capacitance. Thus, the circuitry of the present inventionmay be employed in a variety of integrated circuits, each of which mayhave a unique capacitance associated with the bondpad.

It is to be understood that both the forgoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention as claimed. The accompanyingdrawings, which are incorporated in and constitute a part of thespecification, illustrate an embodiment of the invention and togetherwith the general description, serve to explain the principles of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The numerous advantages of the present invention may be betterunderstood by those skilled in the art by reference to the accompanyingfigures in which:

FIG. 1 depicts an embodiment of an integrated circuit known to the art;

FIG. 2 depicts an embodiment of a current conveyor in accordance withthe present invention;

FIG. 3 depicts an embodiment of a negative capacitance generator 300with two current conveyors in accordance with the present invention;

FIG. 4 depicts an embodiment of active circuitry for generating anegative capacitance in accordance with the present invention; and

FIG. 5 depicts an embodiment of an integrated circuit employing activecircuitry for generating a negative capacitance in accordance with thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the presently preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings.

Referring to FIG. 2, an embodiment of a current conveyor 200 inaccordance with the present invention is shown. Current conveyor 200, athree port device, may be the building block of a negative capacitancegenerator (shown in FIG. 3) of the present invention, with the followingproperties: $\begin{matrix}{\begin{bmatrix}{i1} \\{i2} \\{v3}\end{bmatrix} = {\begin{bmatrix}0 & 0 & 0 \\0 & {- 1} & 0 \\1 & 0 & 0\end{bmatrix}\begin{bmatrix}{v1} \\{i3} \\{v3}\end{bmatrix}}} & \left( {{Equation}\quad 1} \right)\end{matrix}$

From Equation 1, the following equations may be obtained:i1=0i2=−i3v3=v1

From these equations, it may be determined that the current conveyor 200has a high impedance node at Port 1, in which there may be no currentflow. Current conveyor 200 may also have a voltage follower propertythat may transfer the voltage at Port 1 to Port 3 along with a currentflow property that may transfer current from Port 3 through Port 1.

Referring to FIG. 3, an embodiment of a negative capacitance generator300 with two current conveyors in accordance with the present inventionis shown. From an analysis of FIG. 3 and employing well known electricalprinciples, the following relations may be obtained:Iin=Icc+Iloop  (Equation 2)Icc+Iloop=Icap  (Equation 3)Vin=Iloop*R2  (Equation 4)V2=−Iloop*R1  (Equation 5)Icap=V2jωC  (Equation 6)

By combining Equation 2 and Equation 3,Iin=Icap  (Equation 7)

Equation 6 may be written as:Icap=V2/jωC=−Iloop*R1/jωC=−Vin*R1/R2*jωC  (Equation 8)

Equation 7 and Equation 8 may be combined to yieldIIn/Vin=−(R1/R2)*jωC=jωCeff  (Equation 9)

From Equation 9, the effective capacitance into Port 3 of the negativecapacitance or 300 may be determined as:Ceff=−(R1/R2)*C  (Equation 10)

Referring to FIG. 4, an embodiment of circuitry 400 for generating anegative capacitance in accordance with the present invention is shown.It is contemplated that current conveyor 200 of the present inventionmay be implemented through a transistor, such as an n-channel metaloxide silicon field effect transistors (MOSFET). In the embodiment ofemploying a MOSFET, Ports 1-3 of FIG. 2 may refer to the terminals ofthe MOSFET whereby Port 1 may refer to the gate, Port 2 may refer to thedrain, and Port 3 may refer to the source. Consequently, negativecapacitance generator 300 of FIG. 3 may be implemented as shown incircuitry 400 as shown in FIG. 4.

Active circuitry 400 may include a pair of transistors 410-420,resistors 430-440, capacitor 450. Transistor 410 and transistor 420 eachoperate as a current conveyor 200 of FIG. 2. Since Port 1 of FIG. 2 isthe gate of a MOSFET, the current that flows into the drain is equal tothe current that flows out of the source. In some applications of aMOSFET embodiment, the gate to source voltage drop may prevent the gatevoltage from being identically equal source voltage. Thus, in analternative embodiment, multiple MOSFETS may be utilized in parallel,rather than employing a single MOSFET 410-420 to reduce the gate tosource voltage drop closer to zero. For example, a pair of MOSFETtransistors connected in parallel may take the place of transistor 410while another pair of transistors connected in parallel may take theplace of transistor 420. This is advantageous as this may allow the gatevoltage to be approximately equal to the source voltage.

Two bias voltages 460-470 may be utilized to control operation of thecircuitry 400. Bias voltages 460-470 may be coupled to voltage controlsof an integrated circuit in which the circuitry 400 has been included toreduce the bondpad capacitance associated with the integrated circuit.In an advantageous aspect of the present invention, a negativecapacitance may be produced as previously described with respect to thenegative capacitance generator 300 of FIG. 3. The value of the negativecapacitance produced:Ceff=(Resistor 430/Resistor 440)*Capacitor 450

While active circuitry 400 shown in FIG. 4 employs n channel metal oxidesilicon field effect transistors (MOSFETS), it is contemplated that thecircuitry could employ bipolar transistors or gallium arsenidepseudomorphic high-electron mobility transistors (PHEMTS) withoutdeparting from the scope and spirit of the present invention.Additionally, other types of circuits may be employed to generate anegative capacitance as contemplated by one of ordinary skill in the artwithout departing from the scope and intent of the present invention.

An advantageous aspect of active circuitry 400 of the present inventionlies in the adjustability of the negative capacitance produced. Bysimply adjusting the values for resistors 430-440 and capacitor 450, thenegative capacitance produced by the active circuitry may be adjusted.This is advantageous from a manufacturing perspective as the samecircuitry may be manufactured with different component values tocompensate for different bondpad capacitances associated with differenttypes of integrated circuits.

Referring now to FIG. 5, an embodiment of an integrated circuit 500employing active circuitry for generating a negative capacitance inaccordance with the present invention is shown. Similar to theintegrated circuit known to the art shown in FIG. 1, integrated circuit500 may include a plurality of dielectric layers 520-540 and a pluralityof metal layers 550-570. Metal layers may refer to any type of metalutilized in the formation and fabrication of integrated circuits,similarly dielectric materials may include various forms ofnonconductors known to the art.

Negative capacitance circuitry 400 may be fabricated in the siliconsubstrate 510 of the integrated circuit 500. The negative capacitancecircuitry 400 may be coupled to the bondpad 580 via a stack 590. Thestack 590, also known as a via by those with ordinary skill in the art,may run through the metal and dielectric layers from the siliconsubstrate 510 to the bondpad 580. It is contemplated that stack 590 maybe formed of metal or other conducting material and connected to theportion of the equivalent capacitance portion (Ceff) of the negativecapacitance circuitry 400 of FIG. 4.

An amount of negative capacitance produced may be a value, i.e. amagnitude, to compensate for the positive capacitance associated withthe bondpad 580. Advantageously, this amount may reduce the negativeeffects associated with bondpad capacitance and may improve performanceof the integrated circuit 500. Additionally, the value of the negativecapacitance produced by the circuitry 400 of the present invention maybe approximately equal in magnitude to the capacitance associated withthe bondpad 580 whereby magnitude refers to a quantity. For example, thebondpad capacitance may be +10 microFarads as an arbitrary value. Inthis same example, a negative capacitance of −10 microFarads may begenerated by circuitry 400, thus, the magnitude of the negativecapacitance generated would be approximately equal to the magnitude ofthe bondpad capacitance.

In an advantageous aspect of the present invention, the negativecapacitance circuitry 400 may be fabricated within the silicon substrate510 during the manufacture of the integrated circuit. This provides acost-effective method of compensating for the bondpad capacitance.Additionally, the negative capacitance circuitry 400 of the presentinvention may be incorporated within the integrated circuit 500 withoutmodifying the layer structure of the integrated circuit.

It is contemplated that the negative capacitance circuitry 400 may beemployed with a number of different embodiments of integrated circuitsin order to compensate for bondpad capacitance without departing fromthe scope and intent of the present invention. For example, siliconsubstrate may be formed of other materials known to the art. One or morelayers of dielectric material and metal layers may be employed inalternative embodiments of the invention.

It is believed that the system and method and system of the presentinvention and many of its attendant advantages will be understood by theforgoing description. It is also believed that it will be apparent thatvarious changes may be made in the form, construction and arrangement ofthe components thereof without departing from the scope and spirit ofthe invention or without sacrificing all of its material advantages. Theform herein before described being merely an explanatory embodimentthereof. It is the intention of the following claims to encompass andinclude such changes.

1. An integrated circuit, comprising: a substrate; at least one area of dielectric material disposed on said substrate; at least one area of metal material disposed on said substrate; a bondpad associated with said at least one area of dielectric material and said at least one area of metal material; a circuitry for generating a negative capacitance, said circuitry generating said negative capacitance of a value to compensate for a capacitance associated with said bondpad, said active circuitry being coupled to said bondpad.
 2. The integrated circuit as claimed in claim 1, wherein a value of said negative capacitance is approximately equal in magnitude to said capacitance associated with said bondpad.
 3. The integrated circuit as claimed claim 1, wherein said circuitry comprises: at least two transistors; at least two resistors; each resistor of said at least two resistors being coupled to each of said at least two transistors; a capacitor coupled to a first transistor of said at least two transistors and a first resistor of said at least two resistors.
 4. The integrated circuit as claimed in claim 3, wherein said at least two transistors are at least one of bipolar transistors, MOSFETS, and gallium arsenide pseudomorphic high-electron mobility transistors.
 5. The integrated circuit as claimed in claim 3, wherein said negative capacitance generated by said circuitry is dependent upon component values of said at least two resistors and said capacitor.
 6. The integrated circuit as claimed in claim 1, wherein said circuitry is fabricated within the substrate.
 7. An apparatus, comprising: a housing; a substrate disposed within said housing; at least one area of dielectric material disposed on said substrate; at least one area of metal material disposed on said substrate; a bondpad associated with said at least one area of dielectric material and said at least one area of metal material, said bondpad being coupled to said housing; and a circuitry for generating a negative capacitance, said circuitry generating said negative capacitance of a value to compensate for a capacitance associated with said bondpad, said active circuitry being coupled to said bondpad.
 8. The apparatus as claimed in claim 7, wherein said value of said negative capacitance is approximately equal in magnitude to said capacitance associated with said bondpad.
 9. The apparatus as claimed claim 7, wherein said circuitry comprises: at least two transistors; at least two resistors; each resistor of said at least two resistors being coupled to each of said at least two transistors; a capacitor coupled to a first transistor of said at least two transistors and a first resistor of said at least two resistors.
 10. The apparatus as claimed in claim 9, wherein said at least two transistors are at least one of bipolar transistors, MOSFETS, and gallium arsenide pseudomorphic high-electron mobility transistors.
 11. The apparatus as claimed in claim 9, wherein said negative capacitance generated by said circuitry is dependent upon a component values of said at least two resistors and said capacitor.
 12. The apparatus as claimed in claim 11, wherein said negative capacitance generated by said circuitry is dependent upon a ratio of a first resistor to a second resistor multiplied by a value of said capacitor.
 13. The apparatus as claimed in claim 7, wherein said circuitry is fabricated within the substrate.
 14. An apparatus, comprising: a housing; a substrate disposed within said housing; at least one area of dielectric material disposed on said substrate; at least one area of metal material disposed on said substrate; a bondpad associated with said at least one area of dielectric material and said at least one area of metal material, said bondpad being coupled to said housing; and a circuitry for generating a negative capacitance, said circuitry generating said negative capacitance of a value approximately equal in magnitude to a capacitance associated with said bondpad, said active circuitry being fabricated within said substrate and coupled to said bondpad.
 15. The apparatus as claimed claim 14, wherein said circuitry comprises: at least two transistors; at least two resistors; each resistor of said at least two resistors being coupled to each of said at least two transistors; a capacitor coupled to a first transistor of said at least two transistors and a first resistor of said at least two resistors.
 16. The apparatus as claimed in claim 15, wherein said at least two transistors are at least one of bipolar transistors, MOSFETS, and gallium arsenide pseudomorphic high-electron mobility transistors.
 17. The apparatus as claimed in claim 15, wherein said negative capacitance generated by said circuitry is dependent upon component values of said at least two resistors and said capacitor.
 18. The apparatus as claimed in claim 17, wherein said negative capacitance generated by said circuitry is dependent upon a ratio of a first resistor to a second resistor multiplied by a value of said capacitor.
 19. An integrated circuit, comprising: a substrate; at least one area of dielectric material disposed on said substrate; at least one area of metal material disposed on said substrate; a bondpad associated with said at least one area of dielectric material and said at least one area of metal material; means for generating a negative capacitance, said generating means generating said negative capacitance of a value to compensate for a capacitance associated with said bondpad.
 20. The integrated circuit as claimed in claim 19, wherein said value of said negative capacitance is approximately equal in magnitude to said capacitance associated with said bondpad. 